Scan architectures, RT-level scan design, and Boundary Scan (JTAG).

Gate-level faults, fault collapsing, and structural modeling in Verilog.

The book describes on-chip decompression algorithms in Verilog, providing a realistic look at how these impact overall chip area and performance. Key Technical Coverage

The material is structured into two main parts: developing test environments and implementing testable hardware. Key Topics Covered

Are you interested in a specific from the book, like BIST or Boundary Scan , for a more detailed breakdown? Courses Syllabus – Monsoon 2024 - pgadmissions@iiit.ac.in